The emerging need for the current medical devices to achieve immediate visualization and performing diagnostic imaging at real time augurs the demand for high computational power of the associated electronic circuitry. The demand for such a high computational requirement is often met by using software methods to accelerate the computation, which is possible only to a certain extent, impairing the feasibility of real-time imaging and diagnosis.
In this paper, a new method of using digital signal processors (DSPs) with a specialized pipelined vision processor (PVP) embedded at the hardware level to accelerate the routinely time-consuming imaging computation is proposed and validated. A lab prototype is built for the feasibility study and clinical validation of the proposed technique.
This unique architecture of the PVP in a dual-core DSP offers a high-performance accelerated framework along with its large on-chip memory resources, and reduced bandwidth requirement provides as an ideal architecture for reliable medical computational needs. We have taken two sets sample studies from SPECT for validation—27 cases of thyroid medical history and 20 cases of glomerular filtration rate of kidneys. The results were compared with definitive post-scan SIEMENS image analysis software. From the statistical results, it is clearly shown that this method achieved very superior accuracy and 250% acceleration of computational speed.
ANALOG DEVICES DSP BF60
As shown in Figure 1, ADSP BF609 is a dual core-fixed point processor used for embedded vision and real time imaging. The specialty of this processor is due to its unique hardware engine called Pipelined Vision Processor (PVP). This comprises of a set of blocks which operates irrespective of the dual cores and is used to accelerate image processing algorithms and reduce the overall bandwidth requirements.
ADVANTAGES OF PVP
The PVP bundles a set of processing blocks required for high speed 2-Dimensional digital signal processing. The PVP contains a number of highly configurable blocks that provide a broad set of pixel processing features. The Block diagram of PVP is shown in Figure 2.
The EZ kit provided by Analog Devices has the BF609 processor interfaced by a lot of connecting options. The block diagram of the EZ Kit is shown in Figure 3. It has an on board 25 MHz oscillator and can run up to a maximum of 500 MHz.
This section deals with detailed analysis of the methods deployed for the medical image segmentation using the BF609 processor. This is an application with an entry point of commands at Core0 from the CCES. Figure 4 shows how the application is distributed inside the processor. Core0 takes in image frames from the host PC in the form of text file and the segmented image from the Region of Interest is handed over to PVP.
Each configuration register can be manually configured by looking into its structure and locating the specific bits. The above code configures the IIM whose structure is as given in Figure 6.
DEVISED APPROACHES TO MEASURE ACCELERATION
The medical RAW data was acquired by SIEMENS E-CAM and processed into a DICOM image format. To facilitate the time study and parameter estimation by proposed methods, the following two approaches were devised.
RESULTS AND DISCUSSION
Figures 7 and 8 plot the results of computation using the three approaches, showing good visual correlation. To test the hypothesis that the results drawn from the SoC method (M = 6.88, SD = 5.66 for TUR;M = 74.99, SD = 22.94 for GFR) and SIEMENS software (M = 6.96, SD = 5.82 for TUR;M = 74.89, SD = 23.02 for GFR) were equal, a dependent (or paired) samples t-test was performed. Prior to concluding the analysis, the assumption of normally distributed difference scores was examined.
Source: Amrita University
Authors: Murali Ravi | Siva Sankara Sai Sanagapati